This invention relates to semiconductor integrated circuit devices in general and, more particularly, to an improved memory device constructed of a memory array portion to be connected to a peripheral circuit. The memory array portion is formed of field effect transistor cells disposed in a matrix. A method of manufacturing the same is provided.
In a prior art process of forming such structures, plane configurations of a semiconductor substrate, a field insulating film, a floating gate electrode layer, a (control) gate electrode layer, a contact hole, and a metallic wire layer are sequentially formed, as shown in FIGS. 1A-1F. It is noted that the cross-sectional views taken along the plane of line II-II' and III-III' for each of FIGS. 1A-1F are shown in FIGS. 2A-2F and 3A-3F, respectively.
In FIGS. 1F, 2F, and 3F, there is shown a polysilicon gate electrode layer forming gate electrodes 1 providing an address line for each column of the cells in the memory matrix. A source diffusion layer in the substrate forms source diffusion channels 2 disposed in parallel with the gate electrodes 1 to provide a data line for each column of cells in the matrix. A drain diffusion layer forms drain diffusion channels 3 disposed perpendicularly to the gate electrodes 1 and source diffusion channels 2 to provide the address line for each row of the cells in the memory matrix. A source contact hole 4 filled with metal provides an ohmic contact node which connects a source diffusion channel 2 to a peripheral circuit when the data stored in one of the array cells is to be read out. An aluminum wire layer forms lead wires 6 disposed perpendicularly to the gate electrodes 1. Thus, the metallic wire layer forms a data lead wire 6 which connects to a source diffusion channel 2 through the metal-filled source contact hole 4. A second aluminum wire layer forms a second set of lead wires 7 disposed in parallel with the first set of lead wires 6 and connects to a drain diffusion channel 3 through the metal-filled drain contact hole 5 to form a row select lead wire.
A memory cell is produced wherever a drain diffusion channel 3 crosses both a polysilicon gate electrode 1 and a source diffusion channel 2. Such a memory transistor cell is of the stacked-gate structure type having a control gate electrode 1 over a floating gate electrode 8. While the control gate electrode is connected to the column select line, the function of the floating gate is to store charges almost indefinitely. As shown in FIG. 2F, each memory transistor cell has, on a semiconductor substrate 10, a thin floating gate oxide 11, a first layer of polysilicon forming a floating gate electrode 8, a thin control gate oxide 12, and a second layer of polysilicon forming a control gate electrode 1. A field insulating SiO.sub.2 film 9 is disposed on the substrate 10 and is etched therefrom to provide film-free regions above those portions which are to become the source diffusion channels and the drain diffusion channels. Thus, the field insulating layer 9 divides the substrate 10 into a number of predetermined areas in which the memory cells and diffusion channels will be contructed, as well as provides insulating isolation among those cells.
In the following paragraphs, the conventional method of manufacturing a memory device of the nature described above will be explained with reference to FIGS. 1-3. The drawbacks of such a method will be pointed out as background for an explanation of the present invention.
As illustrated in FIGS. 1A, 2A, and 3A, the field insulating film 9 of 7000-8000 .ANG. thickness is selectively formed on the semiconductor substrate 10, and then a thin oxide film 11a (500.ANG.) is formed on the entire surface of the substrate 10. For the sake of convenience, the oxide film 11a is not shown in FIGS. 1A-1F. A 3000 .ANG. thick polysilicon layer 8a is then formed on the substrate 10 over the oxide film 11a, as shown in FIGS. 1B and 2B. The polysilicon layer 8a is selectively removed, by an etching process, to form bands of polysilicon 8b of width "W", as shown in FIG. 1C. The polysilicon bands 8b define the memory array portion constructed of a plurality of FET memory cells, each of which has a gate electrode of a two-layered structure with the polysilicon film 8b representing the bottom floating gate electrode of such a structure. A 600 .ANG. oxide film 12a is then formed on the entire surface of the substrate 10 covering the oxide film 11a, as shown in FIG. 3C, as well as the polysilicon bands 8b, as shown in FIG. 2C. Again, for the sake of convenience, the oxide film 12a is not shown in FIGS. 1C-1F. Over the entire surface of the oxide film 12a, a second layer 1a of polysilicon is formed, as shown in FIGS. 1D, 2D, and 3D. This second polysilicon layer 1a, which has a thickness of about 3000 .ANG., represents the top gate electrode of the two-layered transistor structure of the memory cell.
In order to define contact holes for the source and drain lead wires and gate electrodes for each memory cell, the entire polysilicon film 1a is selectively etched. After this etching process, the control gate electrode 1 will be defined for each memory cell, as shown in FIG. 2F, as well as for the structure of FIG. 3E which does not represent a circuit element. Using the gate electrode 1 as a mask, the oxide film 12a, the polysilicon bands 8b, and the oxide film 11a are successively etched to respectively form the control gate oxide 12, the floating gate electrode 8, and the floating gate oxide 11 in this order under the gate electrode 1. It is to be noted that the structure shown in FIG. 3E, which is a sectional view taken along the plane of lines III-III' (FIG. F), does not include a polysilicon band 8b as shown in FIG. 1C. This implies that, since the successive etching process described above is simultaneously performed on the entire substrate surface as defined by the gate mask, the groove resulting in FIG. 3E will be over-etched.
The source diffusion channels 2 and the drain diffusion channels 3 are then formed by a common diffusion technique in the semiconductor substrate, as shown in FIGS. 1E, 2E and 3E. An insulating layer 13 (8000 .ANG.) is then disposed on the entire surface of the substrate 10 covering the diffusion channels as well as the layered gate structures. The insulating layer 13 is then etched so as to form the source contact hole 4 shown in FIG. 3F and the drain contact hole 5 shown in FIG. 2F. Finally, the metallic lead wires 6 and 7 are disposed (or deposited) perpendicularly to the columns of gate electrodes 1 and source diffusion channels 2, both of which are covered by the insulating layer 13 except at the contact holes. The source and drain contact holes 4 and 5 are filled by metal of the metallic lead wires 6 and 7 which form a data lead wire and a row select lead wire, respectively. This results in the completion of the semiconductor memory device.
The emphasis of the present invention is on two structures of the proposed memory device. The first (hereafter referred to as the primary structure) is the stacked-gate memory cell whose sectional view along the plane of line II-II' is shown in FIG. 2F and includes the drain contact hole 5. The second (hereafter referred to as the secondary structure) includes a single-gate electrode layered structure 1 in the vicinity of the connection between the metallic lead wire 6 and the source diffusion channel 2. Although the secondary structure is not a circuit element, it includes the metallic lead wire 6 which plays the role of transferring data appearing on the source diffusion channel to other peripheral circuits or, simply, to the output terminals. The sectional view taken along the plane of lines III-III' (FIG. 1F) shows the composition of the secondary structure as illustrated in FIG. 3F.
Comparing the two structures of FIGS. 2F and 3F, it is noted that the substrate 10 at the contact hole 4 is over-etched, as previously explained. Therefore, the depth T2 of the source contact hole 4, which is the difference in level between the upper surface of the source diffusion channel 2 of the secondary structure and the lower surface of the metallic lead wire 6, is represented by: ##EQU1##
On the other had, the depth T1 of the drain contact hole 5, which is the difference in level between the upper surface of the substrate 10 and the lower surface of the metallic lead wire 7, is represented by: ##EQU2##
As can be seen, according to the conventional manufacturing method, the depth of the drain contact hole is less than that of the source contact hole. Hence, upon the concurrent formation of the source contact hole 4 and the drain contact hole 5, when one intends to conform the etching depths of both the source and drain contact holes to that of the drain contact hole 5, the source metal contact will not reach the surface of the substrate, resulting in a defective device. On the other hand, when one intends to conform the etching depths to that of the source contact hole 4, the height of the drain metal contact will be increased, disadvantageously, resulting in uneven overall thickness of the structures on the chip which is wasteful of area. Moreover, even if the source contact hole 4 is completely formed, there is still the risk of a disconnection between the metallic lead wires and the semiconductor substrate 10 due to the deep contact holes resulting from excessive etching.